https://bias92.github.io/en/Recent content on Fierce & AggressiveHugo -- 0.147.0enThu, 03 Sep 2026 00:00:00 +0000https://bias92.github.io/en/posts/digital-logic-circuits/Wed, 02 Sep 2026 00:00:00 +0000https://bias92.github.io/en/posts/digital-logic-circuits/Lecture notes for Digital Logic Circuits based on Floyd: analog and digital quantities, logic levels, pulses and periodic waveforms, the clock and timing diagrams, NOT, AND and OR, the comparator, adder, encoder and decoder, registers and counters, and the tablet bottling system that ties the blocks together.https://bias92.github.io/en/posts/signals-and-systems/Wed, 02 Sep 2026 00:00:00 +0000https://bias92.github.io/en/posts/signals-and-systems/Lecture notes for Signals and Systems based on Soliman &amp; Srinath: the definition of a signal, continuity and the value at a discontinuity, the rectangular pulse, continuous-time versus discrete-time, periodic signals and sinusoids, harmonics, and harmonically related complex exponentials.https://bias92.github.io/en/posts/llvm-1-licm/Mon, 31 Aug 2026 00:00:00 +0000https://bias92.github.io/en/posts/llvm-1-licm/LLVM LICM moves an invariant multiplication and addition from a loop body into its preheader. A C-to-IR diff shows how invariant operands, memory effects, and the zero-trip path determine whether hoisting is legal.https://bias92.github.io/en/posts/llvm-0-ir-pipeline/Tue, 25 Aug 2026 00:00:00 +0000https://bias92.github.io/en/posts/llvm-0-ir-pipeline/Starting from the difference between interpreters, JITs, and AOT compilers, emit LLVM IR from C with clang, decode it, and follow the compilation pipeline down through assembly to an executable. Observe how optimization passes rewrite the IR via an -O0 vs -O1 diff, and record the optnone attribute that makes opt silently do nothing.https://bias92.github.io/en/posts/cuda-5-concurrency/Sat, 22 Aug 2026 00:00:00 +0900https://bias92.github.io/en/posts/cuda-5-concurrency/How data copies and kernel execution are placed in the same time window, explained in the order host and device memory, pinned memory, cudaMemcpyAsync, stream, and chunk.https://bias92.github.io/en/posts/cuda-4-unified-memory/Thu, 13 Aug 2026 00:00:00 +0000https://bias92.github.io/en/posts/cuda-4-unified-memory/How the CPU and GPU share one memory allocation, explained through virtual addresses, data placement and migration, synchronization, and cache coherence, and applied to the actual device attributes of Jetson AGX Orin.https://bias92.github.io/en/posts/mit-6.5930-l02/Sat, 18 Jul 2026 00:00:00 +0900https://bias92.github.io/en/posts/mit-6.5930-l02/Complete L02 notes: accelerator design methodology, tensors and Einsum, iteration spaces, memory traffic, compute intensity, Roofline analysis, CNN convolution, and mapping fully connected layers to GEMV/GEMM.https://bias92.github.io/en/posts/cuda-3-shared-memory/Tue, 14 Jul 2026 00:00:00 +0000https://bias92.github.io/en/posts/cuda-3-shared-memory/Global memory coalescing, shared memory tiling, bank conflicts with padding and swizzle, occupancy, warp divergence and predication, and four stages of reduction, explained by how the code works.https://bias92.github.io/en/posts/cuda-c-basics/Fri, 29 May 2026 00:00:00 +0000https://bias92.github.io/en/posts/cuda-c-basics/The CUDA C execution model from the ground up: the compilation pipeline, why the 3-stage memory transfer is the bottleneck (with bandwidth numbers), how thread/block/grid schedule onto SM/warp/lane, occupancy, and kernel launch syntax.https://bias92.github.io/en/posts/cuda-2-gpu-genealogy/Fri, 22 May 2026 00:00:00 +0000https://bias92.github.io/en/posts/cuda-2-gpu-genealogy/One line from Tesla (2006) to Rubin (2026): how the NVIDIA SM stayed the same (SIMT, warp = 32, block per SM) while accreting specialized accelerators, how the Tensor Core evolved across five generations, why the consumer and datacenter lines split, and why &lsquo;Rubin&rsquo; is a platform, not just a GPU.https://bias92.github.io/en/posts/cuda-0-gpu-architecture/Fri, 15 May 2026 00:00:00 +0000https://bias92.github.io/en/posts/cuda-0-gpu-architecture/Before CUDA C: the Tesla unified architecture (G80/GT200) from the 2008 IEEE Micro paper. The graphics-to-compute data path (Input Assembler, work distribution, SPA, TPC, SM/SP, SFU/LSU, ROP, DRAM), how the warp and SIMT were born in hardware, clock domains, and how every structure becomes a CUDA term.https://bias92.github.io/en/posts/jetson-flash-troubleshooting/Thu, 19 Mar 2026 00:00:00 +0000https://bias92.github.io/en/posts/jetson-flash-troubleshooting/Documenting the root cause of the tegrarcm_v2 USB write timeout on AMD hosts when flashing a Jetson AGX Orin, and a chroot-based workaround using an Intel laptop with limited RAM.https://bias92.github.io/en/posts/6.5940-lec01-introduction/Sun, 15 Mar 2026 00:00:00 +0000https://bias92.github.io/en/posts/6.5940-lec01-introduction/Notes on MIT 6.5940 (Song Han) Lecture 1. From why DNN efficiency matters through Model Compression, Quantization (AWQ/SmoothQuant/RTN), Sparsity, Edge AI, VLM/VILA, and Hardware Trend.https://bias92.github.io/en/posts/mit-6.5930-l01/Sat, 07 Mar 2026 00:00:00 +0000https://bias92.github.io/en/posts/mit-6.5930-l01/<h2 id="a-word-from-ilya-sutskever-l01-3">A Word from Ilya Sutskever (L01-3)</h2> <p><img alt="Ilya Sutskever Quote" loading="lazy" src="https://bias92.github.io/posts/mit-6.5930-l01/images/L01-3-ilya-quote.png"></p> <p>Early in the lecture there is a quote from Ilya Sutskever.</p> <p>&ldquo;Compute has been the oxygen of deep learning.&rdquo;</p> <p>He said it at the 50th anniversary event for the ACM Turing Award in 2017. Good algorithms alone run nothing. Compute has to back them up. I read this sentence as the shortest answer to why MLSys is needed.</p> <p>Models keep changing. CNNs gave way to Transformers, and structures like MoE and Mamba are common now. Each shift shakes the model-side knowledge, but the problem of running models efficiently on real hardware does not go away. &ldquo;AI-resistant career&rdquo; sounds a bit grand, but I agree that MLSys is a field with staying power.</p>https://bias92.github.io/en/posts/mit-6.5930-hardware-for-deep-learning/Thu, 05 Mar 2026 00:00:00 +0000https://bias92.github.io/en/posts/mit-6.5930-hardware-for-deep-learning/MIT EECS 6.5930 by Prof. Vivienne Sze and Prof. Joel Emer, Hardware Architecture for Deep Learninghttps://bias92.github.io/en/posts/hello-world/Sun, 02 Mar 2025 00:00:00 +0000https://bias92.github.io/en/posts/hello-world/GPU Systems &amp; Deep Learning Hardware